
The circuit uses a clock divider to generate a aprox 1hz clock which drives 4 registers. The register outputs are routed to a full-adder, and the counter value is incremented by 1.
NA
The project uses the external 7-segment display.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | bit0 of increment | bit0 of counter | |
| 1 | bit1 of increment | bit1 of counter | |
| 2 | bit2 of increment | bit2 of counter | |
| 3 | bit3 of increment | bit3 of counter | |
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |