This is a Silicon Art project for TinyTapeout using the custom GDS workflow. A pixel pig artwork and canary token text are directly written as metal polygons on the silicon, visible under a microscope when the chip is fabricated.
The design includes:
.drawing layersImportant DRC note: Art uses .drawing layers (datatype 0) which are the only fabricated layers in TinyTapeout's IHP whitelist. All geometry meets DRC requirements:
The design fits in the 202.08 × 154.98 µm tile area (TinyTapeout IHP 1x1 tile). Pin positions are precisely calculated to match the TinyTapeout IHP template DEF file.
The functional logic is minimal (just for TinyTapeout compatibility):
uo_out[7:0]) are tied to ground (0x00)uio_out[7:0]) are also groundeduio_oe = 0x00)The design maintains connections to all input pins internally to satisfy synthesis requirements, but outputs remain at logic 0 regardless of input values.
No external hardware required. This is primarily an art project.
To view the silicon art after fabrication:
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | in0 | out0 | |
| 1 | in1 | out1 | |
| 2 | in2 | out2 | |
| 3 | in3 | out3 | |
| 4 | in4 | out4 | |
| 5 | in5 | out5 | |
| 6 | in6 | out6 | |
| 7 | in7 | out7 |