227 Tiny MMU
227 : Tiny MMU
- Author: Yuri Honegger
- Description: A tiny MMU for a TTL logic chip cpu
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
This is a TLB (translation lookaside buffer) for a TTL IC breadboard CPU using latch memory.
How to test
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External hardware
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IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | vaddr0 | paddr0 | write_en |
| 1 | vaddr1 | paddr1 | read_valid |
| 2 | vaddr2 | paddr2 | tlb_hit |
| 3 | vaddr3 | paddr3 | |
| 4 | vaddr4 | paddr4 | |
| 5 | vaddr5 | paddr5 | |
| 6 | vaddr6 | paddr6 | |
| 7 | vaddr7 | paddr7 |