13 Borg - Tiny GPU
13 : Borg - Tiny GPU
- Author: Andreas Wendleder
- Description: A RISC-V SoC with a GPU featuring vertex shading, rasterization, and RGB fragment shading
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
Borg is a tiny GPU built around a RISC-V SoC (TinyQV). It renders a 10-frame animation of a rotating RGB triangle, fully self-contained in firmware — no host-side rendering needed.
Architecture
- CPU: TinyQV (RV32EC), runs the application and GPU driver firmware
- GPU core (Borg): FP16 FMA unit with 16 registers, 8-instruction IMEM, MMIO-accessible
- Shaders: Compiled from GLSL → SPIR-V → SPIR-B (custom binary format), embedded in firmware
Rendering Pipeline
- Vertex shader — rotates triangle vertices using sin/cos (computed via LUT)
- Triangle setup — computes edge vectors and 1/area (Newton-Raphson reciprocal on the FPU)
- Rasterization — evaluates edge functions per pixel to determine coverage
- Fragment shader — interpolates per-vertex RGB colors using barycentric coordinates (runs 3× per pixel, once per channel)
- Framebuffer — 16×16 RGB (FP16), written to PSRAM for host readback
Software Stack
The firmware is structured like a Vulkan application:
const borg_vertex_t vertices[3] = {
{ .pos = { ... }, .color = { FP16_ONE, FP16_ZERO, FP16_ZERO } }, // red
{ .pos = { ... }, .color = { FP16_ZERO, FP16_ONE, FP16_ZERO } }, // green
{ .pos = { ... }, .color = { FP16_ZERO, FP16_ZERO, FP16_ONE } }, // blue
};
int main() {
borg_init(vert_borg, ..., frag_borg, ...);
for (int frame = 0; frame < 10; frame++) {
borg_set_angle(&draw, angle);
borg_cmd_draw(&draw, vertices, frame);
borg_present(frame);
angle = fp16_add(angle, FP16_36DEG);
}
}
How to test
In ./fpga:
make triangle
This programs the firmware, boots the FPGA, waits for all 10 frames to render, then reads back 10 PPM images (triangle_00.ppm through triangle_09.ppm).
External hardware
- QSPI PMOD from the Tiny Tapeout store
- For FPGA development: pico-ice board and Raspberry Pi Debug Probe
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Interrupt 0 | UART TX | Flash CS |
| 1 | Interrupt 1 | UART RTS | SD0 |
| 2 | SD1 | ||
| 3 | SCK | ||
| 4 | SD2 | ||
| 5 | SD3 | ||
| 6 | Debug UART TX | RAM A CS | |
| 7 | UART RX | Debug signal / PWM | RAM B CS / PWM |