512 SPI Slave with 8-Register File
512 : SPI Slave with 8-Register File
- Author: Usha
- Description: An industry-grade SPI slave peripheral with an internal 8-byte register file
- GitHub repository
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- Clock: 10000000 Hz
SPI Slave with 8-Register File
How it works
This design implements a standard 4-wire SPI (Serial Peripheral Interface) slave targeting the GlobalFoundries 180nm platform. It contains a synchronous Finite State Machine (FSM) that decodes incoming SPI transactions on SCLK, MOSI, and CS_N.
The core features an internal 8-byte register file. Transactions consist of a 1-byte command phase (specifying a Read/Write bit and a 3-bit register address) followed by a 1-byte data transfer phase. On a write transaction, data is sampled from MOSI and written to the selected register. On a read transaction, data from the internal register is driven out onto MISO. The content of Register 0 is continuously driven out to the dedicated output pins (uo_out) for real-time hardware monitoring.
How to test
To test this design, keep CS_N high initially. Toggle SCLK and ensure MISO remains in a high-impedance or idle state.
- Pull
CS_Nlow to initiate a transaction. - Stream 8 bits on
MOSIsynchronized toSCLKrising edges: Set the first bit to0(Write command) followed by0000000(Address 0). - Immediately stream another 8 bits containing the data payload (e.g.,
0xA5) onMOSI. - Pull
CS_Nback high to commit the byte. - Verify that the external output pins
uo_out[7:0]update to show0xA5.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | unused | reg0_out[0] | SCLK (Input) |
| 1 | unused | reg0_out[1] | MOSI (Input) |
| 2 | unused | reg0_out[2] | CS_N (Input) |
| 3 | unused | reg0_out[3] | MISO (Output) |
| 4 | unused | reg0_out[4] | unused |
| 5 | unused | reg0_out[5] | unused |
| 6 | unused | reg0_out[6] | unused |
| 7 | unused | reg0_out[7] | unused |