353 ttgf jct PoC
353 : ttgf jct PoC
- Author: awayzer JCT
- Description: Naive and very simple implementation of a stream cipher
- GitHub repository
- Open in 3D viewer
- Clock: 500000 Hz
How it works
This project is a naive and very simple implementation of a stream cipher demonstration.
The design contains two internal 8-bit registers:
data_mem— stores the input data.key_mem— stores the encryption key.
The output is generated by XORing the stored data and key values:
uo_out = data_mem ^ key_mem
The module uses uio_in[0] as a synchronization/control signal.
A rising edge on this pin triggers a register update.
The pin uio_in[1] selects which register is updated:
uio_in[1] |
Action |
|---|---|
| 0 | Load ui_in into data_mem |
| 1 | Load ui_in into key_mem |
The bidirectional pins are configured as inputs only, and are never driven by the design.
Pin usage
| Pin | Function |
|---|---|
ui_in[7:0] |
8-bit input data/key bus |
uio_in[0] |
Load trigger (rising edge sensitive) |
uio_in[1] |
Register select |
uo_out[7:0] |
XOR result (data_mem ^ key_mem) |
How to test
- Reset the design by setting
rst_nlow. - Set
uio_in[1] = 0. - Place a byte on
ui_in. - Generate a rising edge on
uio_in[0]to load the value intodata_mem. - Set
uio_in[1] = 1. - Place another byte on
ui_in. - Generate another rising edge on
uio_in[0]to load the value intokey_mem. - Observe that
uo_outequals:
data_mem XOR key_mem
Example:
data_mem |
key_mem |
uo_out |
|---|---|---|
8'hAA |
8'hFF |
8'h55 |
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | data_in[0]/key_in[0] | output[0] | valid |
| 1 | data_in[1]/key_in[1] | output[1] | is_key |
| 2 | data_in[2]/key_in[2] | output[2] | |
| 3 | data_in[3]/key_in[3] | output[3] | |
| 4 | data_in[4]/key_in[4] | output[4] | |
| 5 | data_in[5]/key_in[5] | output[5] | |
| 6 | data_in[6]/key_in[6] | output[6] | |
| 7 | data_in[7]/key_in[7] | output[7] |