192 ECDSA Verification
192 : ECDSA Verification
- Author: Lyra
- Description: Simplified ECDSA digital signature verification module using Verilog
- GitHub repository
- Open in 3D viewer
- Clock: 10000000 Hz
Firmware Signature Verification Accelerator
How it works
The Firmware Signature Verification Accelerator is a hardware security IP designed for secure V2X (Vehicle-to-Everything) communication systems.
This project focuses on verifying the authenticity and integrity of firmware before execution inside automotive electronic systems.
The accelerator uses a cryptographic signature verification process to validate firmware updates.
It prevents unauthorized or tampered firmware from running in the system, improving security against cyber attacks.
Main Functional Blocks
-
Hash Engine
- Generates a secure hash value from incoming firmware data using SHA algorithms.
- Ensures firmware integrity.
-
Signature Verification Core
- Verifies the digital signature using ECC/ECDSA cryptographic methods.
- Confirms firmware authenticity.
-
Key Storage
- Stores trusted public keys used for verification.
-
Control Unit
- Manages verification sequence and operation control.
-
Status Output
- Displays whether firmware is valid or invalid.
Tile Layout Information
The Tiny Tapeout layout contains multiple standard-cell tiles used for implementing:
- Hash computation logic
- ECC arithmetic blocks
- Control FSM
- Memory interface
- Signature verification engine
The total number of tiles depends on synthesis and place-and-route results generated during the OpenLane RTL-to-GDSII flow.
Inputs
| Signal | Description |
|---|---|
| ui_in[7:0] | Firmware data / control input |
| ena | Enable signal |
| clk | System clock |
| rst_n | Active-low reset |
Outputs
| Signal | Description |
|---|---|
| uo_out[7:0] | Verification status output |
| uio_out | Debug/status signals |
How to test
- Apply reset signal (
rst_n = 0) for initialization. - Enable the module using
ena = 1. - Provide firmware data through
ui_in. - Start signature verification process.
- Observe output signals:
- Valid signature → success indication on
uo_out - Invalid signature → failure indication on
uo_out
- Valid signature → success indication on
Simulation Steps
make clean
make
make sim
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Input bit 0 | Output bit 0 | Bidirectional IO 0 |
| 1 | Input bit 1 | Output bit 1 | Bidirectional IO 1 |
| 2 | Input bit 2 | Output bit 2 | Bidirectional IO 2 |
| 3 | Input bit 3 | Output bit 3 | Bidirectional IO 3 |
| 4 | Input bit 4 | Output bit 4 | Bidirectional IO 4 |
| 5 | Input bit 5 | Output bit 5 | Bidirectional IO 5 |
| 6 | Input bit 6 | Output bit 6 | Bidirectional IO 6 |
| 7 | Input bit 7 | Output bit 7 | Bidirectional IO 7 |