579 I2C Master Controller
579 : I2C Master Controller
- Author: Akshaya Institute of Technology
- Description: Simple I2C Master Controller that transmits one byte to a fixed slave address (0x50). Generates START and STOP conditions and provides BUSY, DONE, and ACK status outputs.
- GitHub repository
- Open in 3D viewer
- Clock: 1000000 Hz
How it works
This project implements a simple I2C master controller.
When the START input is asserted, the controller begins transmitting an 8-bit data value serially over the SDA line while generating the SCL clock.
The controller generates:
START condition 8-bit serial transmission STOP condition The BUSY output indicates an active transfer.
How to test
Apply reset. Place an 8-bit value on ui_in. Assert START. Observe SCL and SDA activity. Monitor BUSY until transmission completes.
External hardware
An I2C slave device, logic analyzer, or oscilloscope may be connected to observe SDA and SCL signals.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | START | BUSY | SDA |
| 1 | DATA_BIT1 | DONE | SCL |
| 2 | DATA_BIT2 | ACK | |
| 3 | DATA_BIT3 | ||
| 4 | DATA_BIT4 | ||
| 5 | DATA_BIT5 | ||
| 6 | DATA_BIT6 | ||
| 7 | DATA_BIT7 |