455 SPI Master Slave Communication
455 : SPI Master Slave Communication
- Author: Nevin Philip
- Description: 8-bit Full Duplex SPI Communication using Master and Slave
- GitHub repository
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- Clock: 0 Hz
SPI Master Controller
How it works
This project implements an 8-bit SPI Master Controller using Verilog.
The design accepts 8-bit parallel data through ui_in[7:0]. When the START signal (uio_in[0]) is asserted, the data is loaded into an internal shift register.
A finite state machine (FSM) controls the transmission process using four states:
- IDLE
- LOAD
- TRANSFER
- DONE
The shift register transmits data serially through the MOSI line while generating the SPI clock (SCLK). A chip select (CS) signal is used to indicate active communication. A BUSY signal indicates that transmission is in progress.
How to test
- Apply reset by driving
rst_n = 0. - Load an 8-bit value on
ui_in[7:0]. - Release reset by setting
rst_n = 1. - Assert the START signal using
uio_in[0]. - Observe MOSI output on
uo_out[0]. - Observe SPI clock on
uo_out[1]. - Observe chip select on
uo_out[2]. - Observe busy status on
uo_out[3]. - After 8 bits are transmitted, the FSM returns to IDLE.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | START | MOSI | |
| 1 | MISO | ||
| 2 | SCLK | ||
| 3 | CS | ||
| 4 | DONE | ||
| 5 | MASTER_RX0 | ||
| 6 | SLAVE_RX0 | ||
| 7 |