
Raksha S S
This project implements an 8-bit PWM (Pulse Width Modulation) generator using Verilog. The PWM duty cycle is controlled using the 8-bit input ui_in.
An internal 8-bit counter continuously increments with every clock cycle.
The counter value is compared with the input duty cycle value:
This generates a PWM waveform on uo_out[0].
rst_n = 1).ui_in.uo_out[0].Examples:
ui_in = 64 → 25% duty cycleui_in = 128 → 50% duty cycleui_in = 192 → 75% duty cycleNo external hardware required.
| Pin | Direction | Description |
|---|---|---|
| ui_in[7:0] | Input | PWM duty cycle input |
| uo_out[0] | Output | PWM output signal |
| clk | Input | Clock signal |
| rst_n | Input | Active-low reset |
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Duty Cycle Bit 0 | PWM Output | Unused |
| 1 | Duty Cycle Bit 1 | Unused | Unused |
| 2 | Duty Cycle Bit 2 | Unused | Unused |
| 3 | Duty Cycle Bit 3 | Unused | Unused |
| 4 | Duty Cycle Bit 4 | Unused | Unused |
| 5 | Duty Cycle Bit 5 | Unused | Unused |
| 6 | Duty Cycle Bit 6 | Unused | Unused |
| 7 | Duty Cycle Bit 7 | Unused | Unused |