
This project implements a True Random Number Generator (TRNG) using a Ring Oscillator.
The ring oscillator continuously oscillates because of inverter delay. A sampler captures the oscillating signal using a clock signal. The sampled bits are checked using a health checker to detect repeated patterns. Post-processing improves randomness and generates the final random output bits.
Main modules used:
Simulation commands:
iverilog -o trng_out *.v
vvp trng_out
gtkwave trng.vcd
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Input 0 | Output 0 | Unused |
| 1 | Input 1 | Output 1 | Unused |
| 2 | Input 2 | Output 2 | Unused |
| 3 | Input 3 | Output 3 | Unused |
| 4 | Input 4 | Output 4 | Unused |
| 5 | Input 5 | Output 5 | Unused |
| 6 | Input 6 | Output 6 | Unused |
| 7 | Input 7 | Output 7 | Unused |