578 ECC Scalar Accelerator
578 : ECC Scalar Accelerator
- Author: PM LIKHITH KUMAR AND PRAJWAL T
- Description: Simplified ECC accelerator using Verilog HDL for ASIC implementation
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ECC Scalar Multiplication Accelerator
How it works
This project implements a simplified ECC (Elliptic Curve Cryptography) Scalar Multiplication Accelerator using Verilog HDL.
The design accepts two 8-bit input values through TinyTapeout GPIO pins. These inputs represent simplified ECC operands. The accelerator performs arithmetic operations similar to ECC point processing by adding the two operands and generating a scaled output.
The architecture contains:
- Input interface
- Arithmetic processing block
- Scalar multiplication logic
- Output interface
The design is optimized for ASIC implementation using the SKY130 process and OpenLane physical design flow.
How to test
Inputs are applied using the TinyTapeout input pins.
Inputs
- ui[7:0] -> Operand A
- uio[7:0] -> Operand B
Operation
- Apply input values to Operand A and Operand B.
- The design performs addition of both operands.
- The result is shifted left by one bit to emulate scalar multiplication behavior.
- The processed value appears at the output pins.
Outputs
- uo[7:0] -> Processed ECC output
Example:
- Operand A = 5
- Operand B = 3
- Sum = 8
- Output = 16
External hardware
No external hardware is required.
The design operates entirely inside the TinyTapeout ASIC framework using GPIO interfaces.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Input A bit 0 | ECC output bit 0 | Input B bit 0 |
| 1 | Input A bit 1 | ECC output bit 1 | Input B bit 1 |
| 2 | Input A bit 2 | ECC output bit 2 | Input B bit 2 |
| 3 | Input A bit 3 | ECC output bit 3 | Input B bit 3 |
| 4 | Input A bit 4 | ECC output bit 4 | Input B bit 4 |
| 5 | Input A bit 5 | ECC output bit 5 | Input B bit 5 |
| 6 | Input A bit 6 | ECC output bit 6 | Input B bit 6 |
| 7 | Input A bit 7 | ECC output bit 7 | Input B bit 7 |