
clocks dividers conected together and random stuff try to decode the outpu
in1 in2 are the input of the mux and other ins change the random seed
out s0 to s3 a 4b output of the counter and s4-s9 random seed gen
clock input required
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | |||
| 1 | |||
| 2 | |||
| 3 | |||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |