202 127-stage Coarse-Tapped ADPLL
202 : 127-stage Coarse-Tapped ADPLL
- Author: Catalin Lazar
- Description: A lower-frequency All-Digital PLL featuring a 127-stage tapped structural ring oscillator targeting 125MHz midpoint locking loops on SkyWater 130nm.
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
This project implements a 125 MHz All-Digital Phase-Locked Loop (ADPLL) targeting the SkyWater 130nm process node. It features a structural Digitally Controlled Oscillator (DCO) built using a 127-stage ring loop (1 NAND gating cell and 126 inverters from the sky130_fd_sc_hd library).
A coarse frequency-tapping multiplexer is included to allow switching between the full 127-stage loop (~125 MHz baseline) and a shortened 63-stage loop (~250 MHz baseline) via external pin controls. The feedback loop utilizes a fully synchronous parallel-gated digital divider to minimize clock-to-Q jitter propagation.
How to test
- Apply an active-low reset pulse to
rst_n(ui_in[2]) to initialize the state tracking registers. - Select the input reference clock via
clk_sel(ui_in[1]). Set low to use the internal 50MHz TinyTapeout system clock, or high to feed a custom external clock intoref_clk(ui_in[0]). - Set the coarse frequency selection with
tap_sel(ui_in[3]) to pick the oscillator loop depth. - Configure the 4-bit feedback division ratio bus
div_sel(ui_in[7:4]) to evaluate locking steps and track the output clock frequency viaclk_out(uo_out[0]) and the raw high-speed monitor pindco_clk_raw(uo_out[1]).
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ref_clk | clk_out | unused_uio0 |
| 1 | clk_sel | dco_clk_raw | unused_uio1 |
| 2 | rst_n | status | unused_uio2 |
| 3 | tap_sel | unused_uo3 | unused_uio3 |
| 4 | div_sel[0] | unused_uo4 | unused_uio4 |
| 5 | div_sel[1] | unused_uo5 | unused_uio5 |
| 6 | div_sel[2] | unused_uo6 | unused_uio6 |
| 7 | div_sel[3] | unused_uo7 | unused_uio7 |