
This design translates one 4-bit input into a 7-segment HEX glyph pattern.

The additional display reference photos are available in docs/extra-img.
Functional pipeline:
ui[3:0]: HEX nibble
ui[4]: display_enable
ui[5]: blank
ui[6]: lamp_test
ui[7]: decimal point input
uo[6:0]: segments {a,b,c,d,e,f,g}
uo[7]: decimal point output
uio[0]: active_low_mode
uio_out[7:4]: status flags
cd test
make
cd test
iverilog -o sim_bcd_verify.vvp -I ../src \
../src/project.v \
../src/bcd_to_7seg_decoder.v \
../src/seg_display_control.v \
../src/seg_output_mode.v \
tb_verify.v
vvp sim_bcd_verify.vvp
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | HEX bit 0 | Segment g | Active-low mode (1=common-anode, 0=common-cathode) |
| 1 | HEX bit 1 | Segment f | Reserved |
| 2 | HEX bit 2 | Segment e | Reserved |
| 3 | HEX bit 3 | Segment d | Reserved |
| 4 | Display enable | Segment c | valid digit active |
| 5 | Blank | Segment b | invalid digit active |
| 6 | Lamp test | Segment a | display on |
| 7 | Decimal point input | Decimal point output | active-low mode echo |