
Verilog
run make -B
N/A
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | compare_value[0] | count[0] | edge_detect |
| 1 | compare_value[1] | count[1] | overflow |
| 2 | compare_value[2] | count[2] | match_status |
| 3 | compare_value[3] | count[3] | freeze_status |
| 4 | compare_value[4] | count[4] | signal_in |
| 5 | compare_value[5] | count[5] | enable |
| 6 | compare_value[6] | count[6] | clear |
| 7 | compare_value[7] | count[7] | freeze_on_match |