201 UART Smart I/O Hub
201 : UART Smart I/O Hub
- Author: NAVEEN KUMAAR S
- Description: IEEE SNK_UART-controlled 64-channel PWM hub with banked outputs, internal modulation engine, ALU datapath, and sequencer.
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
This design is a UART-controlled smart I/O hub built around a 64-channel PWM engine.
UART commands arrive on ui_in[0] using a standard 8N1 receiver. The command decoder can write PWM duty cycles, set the prescaler, and load internal modulation registers.
The 64 PWM channels are divided into banks of 8:
ui_in[6:4]selects which bank appears onuo_out- the next bank appears on
uio_out ui_in[7]switchesuio_outto a status page instead of PWM output
The upper 8 channels are reserved for live internal modulation:
- a free-running phase counter
- a small LFSR-style pattern source
- an add/multiply datapath
- a status pattern byte
This gives the design a practical purpose on a PCB while also keeping enough parallel logic to make good use of a 1x2 Tiny Tapeout floorplan.
How to test
- Connect a UART source to
ui_in[0] - Set
ui_in[1] = 1to enable command handling - Set
ui_in[6:4]to choose the output bank - Keep
ui_in[7] = 0to show PWM data onuio_out - Apply reset using
rst_n
Example commands:
0x80+ duty byte → set PWM channel 00x81+ duty byte → set PWM channel 10x88+ duty byte → set PWM channel 80x89+ duty byte → set PWM channel 90xC0+ byte → set prescaler0xC1+ byte → set ALU input A0xC2+ byte → set ALU input B0xC3+ byte → set phase seed0xC4+ byte → set LFSR seed
Expected output: the selected PWM bank appears on uo_out, the next bank appears on uio_out, and the status page appears on uio_out when ui_in[7] = 1.
External hardware
- USB-to-UART adapter or microcontroller for command input
- Oscilloscope or logic analyzer for observing PWM outputs
No additional external hardware is required for basic operation.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | UART RX | PWM output bit 0 | Secondary PWM/status bit 0 |
| 1 | Command enable | PWM output bit 1 | Secondary PWM/status bit 1 |
| 2 | Sequencer enable | PWM output bit 2 | Secondary PWM/status bit 2 |
| 3 | Clear registers | PWM output bit 3 | Secondary PWM/status bit 3 |
| 4 | PWM bank select bit 0 | PWM output bit 4 | Secondary PWM/status bit 4 |
| 5 | PWM bank select bit 1 | PWM output bit 5 | Secondary PWM/status bit 5 |
| 6 | PWM bank select bit 2 | PWM output bit 6 | Secondary PWM/status bit 6 |
| 7 | Debug/status page enable | PWM output bit 7 | Secondary PWM/status bit 7 |