15 Programmable Clock Router (IEEE)
15 : Programmable Clock Router (IEEE)
- Author: AISWARYA VM , GAUTHAM P NAIR , LAKSHMI NAIR
- Description: 8-channel programmable clock divider using a 16-bit counter and configurable routing
- GitHub repository
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- Clock: 0 Hz
How it works
The design implements an 8-channel programmable clock router.
A 16-bit internal counter runs on the system clock and generates multiple divided clock signals. Each output channel is connected to a configuration register that selects one of the counter bits, effectively choosing a clock division ratio.
The user programs each output by:
- Selecting the output channel using ui[2:0]
- Providing the desired division ratio using ui[6:3]
- Triggering a write using ui[7]
Each output then continuously generates the selected divided clock signal independently.
How to test
- Apply reset to initialize the system.
- Select an output channel using ui[2:0].
- Set a division value (0–15) on ui[6:3].
- Pulse ui[7] high to store the configuration.
- Observe the corresponding uo_out pin toggling at a divided clock frequency.
Repeat for different channels with different division values and verify that each output runs at a different frequency.
External hardware
No external hardware is required. Outputs can be observed directly using a logic analyzer, oscilloscope, or FPGA/Vivado waveform simulation.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Address bit 0 | Clock output 0 | |
| 1 | Address bit 1 | Clock output 1 | |
| 2 | Address bit 2 | Clock output 2 | |
| 3 | Data bit 0 (LSB) | Clock output 3 | |
| 4 | Data bit 1 | Clock output 4 | |
| 5 | Data bit 2 | Clock output 5 | |
| 6 | Data bit 3 (MSB) | Clock output 6 | |
| 7 | Write strobe | Clock output 7 |