420 SUBLEQ CPU IEEE
420 : SUBLEQ CPU IEEE
- Author: Touka Szulc
- Description: A type of OISC (One Instruction Set Computer).
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- Clock: 0 Hz
How it works
SUBLEQ (SUbtract and Branch if Less than or EQual to zero) is a type of OISC (One Instruction Set Computer) architecture.
It has only one instruction of the form:
SUBLEQ A B C
Equivalent to this pseudocode:
mem[B] = mem[B] - mem[A]
if mem[B] <= 0 then goto C\
By compounding instructions it is capable of doing other operations, such as addition.
How to test
This module requires a RP2040 or similar connected to the input and output ports to act as an external 16-bit memory (RAM).
A read request from the CPU triggers the "read_latch" ouput for one cycle, with the first LSB (least significant byte) sent via the output pins. Which is followed by the MSB (most significant byte) in the next cycle. The CPU expects the contents of the address to be returned via the input pins in the same order.
Similarly, a write request from the CPU triggers the "write_latch" output for one cycle, in the same manner as above. However with an additional 2 cycles for the value to assign at the address. The CPU does not expect a value from the input ports.
External hardware
RP2040
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Data input (bit 0) | Data output (bit 0) | Memory read latch |
| 1 | Data input (bit 1) | Data output (bit 1) | Memory write latch |
| 2 | Data input (bit 2) | Data output (bit 2) | Memory clock |
| 3 | Data input (bit 3) | Data output (bit 3) | Memory reset |
| 4 | Data input (bit 4) | Data output (bit 4) | |
| 5 | Data input (bit 5) | Data output (bit 5) | |
| 6 | Data input (bit 6) | Data output (bit 6) | |
| 7 | Data input (bit 7) | Data output (bit 7) |