972 IEEE PWM Generator
972 : IEEE PWM Generator
- Author: Maria Jose Huiza
- Description: 2-bit PWM generator with configurable duty cycle via reference bits
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
This project implements a 2-bit PWM (Pulse Width Modulation) generator. It uses a free-running
2-bit counter that increments on every rising clock edge. The PWM output is driven high whenever
the counter value is less than the configured reference value (ref_bits), and low otherwise.
This produces a periodic signal with a duty cycle determined by ref_bits:
| ref_bits | Duty Cycle |
|---|---|
| 0 | 0% |
| 1 | 25% |
| 2 | 50% |
| 3 | 75% |
The counter and output are reset to 0 when the active-low reset signal (rst_n) is asserted.
How to test
- Assert
rst_nlow briefly to reset the module, then release it high. - Set
ui[1:0]to the desired reference value (0–3) to select the duty cycle. - Observe the PWM output on
uo[0]— it will toggle according to the duty cycle table above. - Change
ui[1:0]at runtime to dynamically adjust the duty cycle.
Note:
ui[3:2](state_bits) are connected to the submodule input but are not used in the current logic. Leave them at0unless repurposed in a future revision.
External hardware
No external hardware is required. The PWM output on uo[0] can be connected directly to:
- An LED (with appropriate current-limiting resistor) to observe brightness changes with duty cycle
- A low-pass RC filter to produce an analog voltage proportional to the duty cycle
- A motor driver or other PWM-controlled peripheral
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | PWM reference (duty cycle), bit 0 (LSB) | PWM output signal | |
| 1 | PWM reference (duty cycle), bit 1 (MSB) | ||
| 2 | State bits, bit 0 (LSB) [unused internally] | ||
| 3 | State bits, bit 1 (MSB) [unused internally] | ||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |