128 SPI Memory Test
128 : SPI Memory Test
- Author: James Ashie Kotey
- Description: SPI RAM reader with VGA timing output
- GitHub repository
- Open in 3D viewer
- Open in VGA Playground
- Clock: 25000000 Hz
How it works
This design combines two IP blocks:
- SPI memory controller (
spi_mem_ctrl): A small FSM that reads bytes from an external SPI RAM using command0x03(read) plus a 16-bit address. It drivescs_n,sck, andmosi, samplesmiso, and exposesbusy/validalong with the received byte. - VGA timing core (
vga_sync): Generates 640x480 @ 60 Hz timing. It produceshsync,vsync,display_on, and pixel coordinates (screen_hpos,screen_vpos).
ui_in[0] selects the mode:
- SPI test mode (
ui_in[0]=0):uo_outoutputs the raw SPI byte.ui_in[1]is a start pulse,ui_in[2]is last, andui_in[7:4]select the high address nibble. - VGA mode (
ui_in[0]=1):uo_outoutputs VGA timing + 2-bit RGB (6-bit color). Bytes fetched from SPI are latched intopixel_col.
How to test
- Provide a stable clock and active-low reset (
rst_n). - SPI mode: set
ui_in[0]=0, pulseui_in[1]for one cycle, setui_in[2]for single-byte read, and setui_in[7:4]for address high nibble. Observeuio_out[7:5]for{busy, valid, last}and read the byte onuo_outwhenvalidgoes high. - VGA mode: set
ui_in[0]=1, feed a 25.175 MHz pixel clock, and observeuo_outforHS,VS, and 2-bit RGB.
Use the cocotb test in test/ to exercise the SPI path in simulation.
External hardware
- SPI RAM compatible with 23LC512 read protocol (or a simulator providing
miso). - VGA connector or display interface to observe
hsync/vsynctiming (optional for simulation).
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | MODE (0=SPI, 1=VGA) | SPI_DATA[0] / VGA_R1 | SPI_CS_N |
| 1 | SPI_START | SPI_DATA[1] / VGA_G1 | SPI_SCK |
| 2 | SPI_LAST | SPI_DATA[2] / VGA_B1 | SPI_MOSI |
| 3 | SPI_RST | SPI_DATA[3] / VGA_VSYNC | SPI_MISO |
| 4 | ADDR_HI[0] / VGA_RST | SPI_DATA[4] / VGA_R0 | SPI_DATA[6] |
| 5 | ADDR_HI[1] | SPI_DATA[5] / VGA_G0 | SPI_DATA[7] |
| 6 | ADDR_HI[2] | SPI_DATA[6] / VGA_B0 | SPI_VALID |
| 7 | ADDR_HI[3] | SPI_DATA[7] / VGA_HSYNC | SPI_BUSY |