A cascade of NMOS and capacitors perfomr a delay line.
A two-phase non-overlapping clock is applied to DIN_0 and DIN_1.
A 1Vpp audio signal is applied to UA_0. A summing amplifier is connected to analog outputs UA_1 and UA_2.
# | Input | Output | Bidirectional |
---|---|---|---|
0 | PHASE_1 | ||
1 | PHASE_2 | ||
2 | |||
3 | |||
4 | |||
5 | |||
6 | |||
7 |
ua | analog | Description |
---|---|---|
0 | 11 | AIN |