This is an experiment. A 512-bit shift register (SR) implemented using D latches rather than D flip flops. The shift logic relies on a single pulse rippling along the shift register, from the output latch towards the input latch. The SR has one input, one output, and an edge-triggered control signal that controls the shift update. The SR shifts on either a rising or a falling edge of the control signal.
Shift zeros into the SR until it contains all zeros. Then shift in any sequence of 1s and 0s and observe it appear on the output of the SR after 512 transitions of the control signal.
No external hardware required.
# | Input | Output | Bidirectional |
---|---|---|---|
0 | shift register input | shift register output | |
1 | shift control (edge-triggered) | ||
2 | |||
3 | |||
4 | |||
5 | |||
6 | |||
7 |