The goal of our design is to be able to show different RTL designs on a real chip in our lectures. Therefore, an internal multiplexer selects different projects. The multiplexer is controlled by uio_in[1:0]. The following designs can be selected:
Since we only have 8 bit input and output, an internal logic is responsible for taking the inputs in 8 bit chunks and outputting the results in 8 bit chunks. This logic can be used as follows:
Note that the overflows of both adders are always brought out to uio_out[7:6] to allow measurements. A reset upon changing the design is required to ensure valid results
No external hardware is strictly required. Since the goal of both adders is to measure the difference in execution speed, an oscilloscope is helpful. The decoder for the coin acceptor was designed for the HX-916
# | Input | Output | Bidirectional |
---|---|---|---|
0 | Multiplexed to all designs (refer to documentation for details) | Multiplexed from all designs (refer to documentation for details) | Select design (input) |
1 | ... | ... | Select design (input) |
2 | ... | ... | start_calc |
3 | ... | ... | output_result |
4 | ... | ... | unused |
5 | ... | ... | unused |
6 | ... | ... | overflow bit of RCA (output) |
7 | ... | ... | overflow bit of CLA (output) |