9 tt_um_scisneros29_BCR
9 : tt_um_scisneros29_BCR
- Author: Juan, Cris y Santi
- Description: Banco (BCR) de registros
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
Proyect files
| File | Description | Primary function |
|---|---|---|
| Memory Bank | Memory bank module | Data storage and read/write logic using enables |
| TOP | Top module of the memory bank | An interface that enables connections to the simulator to conduct GDS tests |
The project consists of a memory bank named “tt_um_BCR” that can store 8 data bits, each 8 bits in length; these can be accessed via the ‘we’ and “re” enable inputs, which makes the process easier since read and write operations are independent.
Cell usage by category
| Category | Cells | Count |
|---|---|---|
| Fill | decap fill | 3244 |
| Tap | tapvpwrvgnd | 225 |
| Misc | dlygate4sd3 conb | 80 |
| Flip Flops | dfrtp | 72 |
| Multiplexer | mux2 | 64 |
| Combo Logic | and3b nor3b a22o a221o o21a and4b or4b and4bb | 57 |
| Clock | clkdlybuf4s25 | 31 |
| Buffer | clkbuf buf | 18 |
| OR | or3 or4 | 9 |
| AND | and2 and3 and4 | 5 |
| NOR | nor2 nor3 | 2 |
| Inverter | inv | 1 |
339 total cells (excluding fill and tap cells)
How to test
The module has a total of 7 inputs: Clock input (clk) Reset input (rst_n) Write pointer input (addr_w) Read pointer input (addr_r) Data input (data_in) Write enable input (we) Read enable input (re)
And 1 output: Output of the data to be read (data_out)
It works as follows: It consists of a simple 8-bit data register with a capacity of 8 bits.
When you want to store data via the data_in input, the write signal (we) is activated, and the address where the data is to be stored is provided via the addr_w input.
When you want to view or read data that has already been stored, the read signal (re) is activated, and the address of the data to be read is provided via the addr_r input.
External hardware
No external hardware was needed.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | data_in0 | data_out0 | addr_w0 |
| 1 | data_in1 | data_out1 | addr_w1 |
| 2 | data_in2 | data_out2 | addr_w2 |
| 3 | data_in3 | data_out3 | addr_r0 |
| 4 | data_in4 | data_out4 | addr_r1 |
| 5 | data_in5 | data_out5 | addr_r2 |
| 6 | data_in6 | data_out6 | we |
| 7 | data_in7 | data_out7 | re |