331 Delta-Sigma ADC Decimation Filter
331 : Delta-Sigma ADC Decimation Filter
- Author: Alexander Sheldon
- Description: Decimation filter for output of a delta-sigma ADC.
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
Digital low pass and decimation filter for use at the output of a delta-sigma ADC. Analog will hopefully be included on the next shuttle.
How to test
Input 1 bit data on ui_in[0] at 50MHz representing the output of a delta-sigma modulator Will generate 16 bit data on the GPIOs at 50MHz/64=781.25kHz
External hardware
TBD
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | dec_in | mux_out[0] | div_clk8x |
| 1 | mux_out[1] | ||
| 2 | mux_out[2] | div_clk | |
| 3 | mux_out[3] | ||
| 4 | mux_out[4] | ||
| 5 | mux_out[5] | ||
| 6 | mux_out[6] | ||
| 7 | mux_out[7] |