
A two digit 7-segment display shows a hex representation of the 8-bit value provided on ui[7:0]. Byte ui[7:0] is latched when the write enable signal on uio[0] is high at a rising clock edge. The display is driven continuously by uo[6:0] with uo[7] controlling which digit is being driven (0=left digit, 1=right digit).
Connect the 7-segment display to the uo[6:0] outputs (segment 'a' is uo[0], ..., segment 'g' is uo[6]). Connect the uo[7] signal to a switch to control which digit is being driven.
Connect wires to the ui[7:0] and uio[0] inputs. Ground all of ui[7:0] and set uio[0] low and verify that the display is 00. Pull ui[0] high and briefly pull uio[0] high and the display value should change to 01.
Pull ui[0] low again and displayed value should not change; now also pull uio[0] high and the display should return to 00.
Use this two digit 7-segment display (or this one) to test the project.
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Byte to display on 7-segment display (rightmost / low order bit) | 7-segment display (segment a) | write enable (1=latch byte value on ui[7:0] and display it, 0=ignore ui[7:0] and keep displaying the current value) |
| 1 | Byte to display on 7-segment display (next bit) | 7-segment display (segment b) | |
| 2 | Byte to display on 7-segment display (next bit) | 7-segment display (segment c) | |
| 3 | Byte to display on 7-segment display (next bit) | 7-segment display (segment d) | |
| 4 | Byte to display on 7-segment display (next bit) | 7-segment display (segment e) | |
| 5 | Byte to display on 7-segment display (next bit) | 7-segment display (segment f) | |
| 6 | Byte to display on 7-segment display (next bit) | 7-segment display (segment g) | |
| 7 | Byte to display on 7-segment display (leftmost / high order bit) |