13 4-bit Multiplier :: Quicker, easier and cheaper to make your own chip!

13 : 4-bit Multiplier

Author: Nick Pham, Nathan Macapinlac

Description: 4-bit multiplier for NYU's digital logic course's Lab 4

Clock: 0 Hz

Above is a diagram that represents a 4-bit multiplier, which takes in two 4-bit integers and outputs a single 8-bit integer.

This was created using a manual structural design. We utilized a 1-bit full adder module in our implementation.

AND-Gates are utilized to multiply each bit of input m with each bit of input q.
We align partial products diagonally to mimic that of manual binary multiplication.
We use 1-bit Full Adders to add products and handle carries.
The outputs of the Full Adders eventually went to the bits of our output p which is an 8-bit integer.

Creating your own test cases:

# Example
# TEST CASE #0 -> 0 * 1
dut.ui_in.value = 0b00000001
await ClockCycles(dut.clk, 1)
assert dut.uo_out.value = 0b00000000

N/A

#	Input	Output
0	m[0]	p[0]
1	m[1]	p[1]
2	m[2]	p[2]
3	m[3]	p[3]
4	q[0]	p[4]
5	q[1]	p[5]
6	q[2]	p[6]
7	q[3]	p[7]

Input

Output

Bidirectional

m[0]

p[0]

m[1]

p[1]

m[2]

p[2]

m[3]

p[3]

q[0]

p[4]

q[1]

p[5]

q[2]

p[6]

q[3]

p[7]

Chip location

13 4-bit Multiplier