
This project implements a simple decimal counter that counts from 0 to 9 and displays the current count on a 7-segment display.
The design uses a 4-bit counter that increments on each clock edge. When the counter reaches 9, it automatically wraps back to 0 on the next clock cycle. The counter value is decoded into 7-segment display patterns using a combinational logic decoder.
The design expects a 1 Hz clock input (configured via clock_hz: 1 in info.yaml).
You will need:
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ui_unused_0 | Segment A | uio_unused_0 |
| 1 | ui_unused_1 | Segment B | uio_unused_1 |
| 2 | ui_unused_2 | Segment C | uio_unused_2 |
| 3 | ui_unused_3 | Segment D | uio_unused_3 |
| 4 | ui_unused_4 | Segment E | uio_unused_4 |
| 5 | ui_unused_5 | Segment F | uio_unused_5 |
| 6 | ui_unused_6 | Segment G | uio_unused_6 |
| 7 | ui_unused_7 | Decimal Point | uio_unused_7 |