547 4-bit CLA
547 : 4-bit CLA
- Author: Wei Zhang
- Description: A 4 bit carry look-ahead adder
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
This is a 4-bit CLA. It can be used to construct the adder with higher bits.
How to test
The design has 3 input ports: a, b and ci It has 2 output ports: s and co a: an addend. b: the other addend. ci: the carry signal for the input. s: the output sum. co: the carry signal for the output.
This project was tested by an U250 FPGA.
External hardware
List external hardware used in your project (e.g. PMOD, LED display, etc), if any No external hardware
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | a[0] | s[0] | ci |
| 1 | a[1] | s[1] | |
| 2 | a[2] | s[2] | |
| 3 | a[3] | s[3] | |
| 4 | b[0] | co | |
| 5 | b[1] | ||
| 6 | b[2] | ||
| 7 | b[3] |