614 AXIS_UART_TTO
614 : AXIS_UART_TTO
- Author: K Shreenidhi, Punith Roy S, Krishna Negi
- Description: Data generated by the AXI-Stream master is pushed into the FIFO. From the FIFO,to the UART transmitter,and to the UART receiver which reconstructs the parallel data, and outputs it.
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
This project bridges a parallel AXI-Stream interface with a serial UART communication protocol. Data is received from an AXI master, stored in an 8-byte synchronous FIFO to handle clock domain and speed mismatch, then serialized and transmitted over UART. A loopback UART receiver is integrated to validate data integrity.
Flow of data:
-
AXI Input Stage: AXI master asserts axis_valid with data on axis_data. When m_axis_ready is high, data is accepted and written to FIFO.
-
FIFO Buffering: FIFO stores incoming bytes until the UART transmitter is ready to send. Read and write can occur simultaneously.
-
UART Transmission:
a) Each byte is serialized at 115200 baud.
b) Start bit (0), data bits (8), parity bit, and stop bit (1) are sent.
c) tx_data_ready indicates when UART can accept new data.
- UART Reception:
a) Receiver detects start bit, samples bits at mid-baud intervals.
b) Extracts data, verifies parity, and asserts rx_valid.
c) If parity check fails, parity_err is asserted for one clock.
- Loopback Communication: The transmitted UART data (uart_tx) is internally connected to the receiver’s rx line, allowing full system verification.
How to test
You can test the design in two ways:
- Simulation (Testbench)
Provide sequential 8-bit ASCII values to the AXI input (axis_data, axis_valid).
Monitor UART TX output to see data serialized.
Observe rx_data and rx_valid to verify that the UART receiver reconstructs the same data.
- Hardware
Use a UART terminal at 115200 baud rate.
Send data through the AXI interface (or mapped IO pins).
View the corresponding UART output on TX pin.
Since the design includes loopback, received data is automatically validated and made available on output pins.
A successful test shows the same data at rx_data that was sent via axis_data.
External hardware
No external hardware is necessary to verify core functionality.
The project is designed to be fully testable on-chip using the internal UART loopback.
External UART or LEDs can be added only if real-time debugging is required.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | a[0] | b[0] | c[0] |
| 1 | a[1] | b[1] | c[1] |
| 2 | a[2] | b[2] | c[2] |
| 3 | a[3] | b[3] | c[3] |
| 4 | a[4] | b[4] | c[4] |
| 5 | a[5] | b[5] | c[5] |
| 6 | a[6] | b[6] | c[6] |
| 7 | a[7] | b[7] | c[7] |