Tiny Tapeout > Tiny Tapeout Chips > Tiny Tapeout SKY 25b > 559 Manchester Encode/Decode with built-in 5X PLL
559 Manchester Encode/Decode with built-in 5X PLL
559 : Manchester Encode/Decode with built-in 5X PLL
- Author: patrick-lin-git
- Description: Manchester Encode/Decode
- GitHub repository
- Open in 3D viewer
- Clock: 25000000 Hz
Manchester Encode/Decode
### Author: Patrick Lin (https://github.com/patrick-lin-git)
### Description: Machester Encode/Decode
### Language: Systemverilog
How it works
This chip perform machester encode or decode function that conver a paralle 8 bit of data to serial bit stream. Here below is the pin function:
INPUT:
CLK100M 100MHz Clock is needed when DIR pin is 0. if DIR is 1, keep this input low.
DIR Control data conversion direction, 1: Encode (TX) / 0: Decode (RX)
HALT Control Halt or normal, 1: STOP Paralle/Serial Conversion / 0: Normal Function, do auto convert repeatly
BIST 1: Enter BIST Mode / 0: Normal Mode
RXD if DIR is 0, this should connect the counter part chip. Keep low if DIR is 1.
OUTPUT:
DBGO Internal Debug Singal Output
TXD Valid when DIR is 1, Keep floating if DIR is 0.
How to test
During BIST Mode, all bi-directional IO pin will become input. DBGO[0] will refect the compare error if TX to Rx loopback doesn't match.
External hardware
This chip require two clock
25MHz
100MHz
8 Bi-directional pins might be input or output mode depends on the DIR pin setting.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | CLK100M | DBG_OUT0 | IO0 |
| 1 | DIR | DBG_OUT1 | IO1 |
| 2 | HALT | DBG_OUT2 | IO2 |
| 3 | BIST | DBG_OUT3 | IO3 |
| 4 | PLL_EN | DBG_OUT4 | IO4 |
| 5 | DBG_SEL0 | DBG_OUT5 | IO5 |
| 6 | DBG_SEL1 | DBG_OUT6 | IO6 |
| 7 | MCHT_RXD | MCHT_TXD | IO7 |