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491 : Baud-Rate PAM4 Clock and Data Recovery (CDR)

Author: Soumobrata Ghosh

Description: A baud-rate PAM4 CDR with Mueller–Müller phase detector, PI loop filter, and digital DCO.

Clock: 50000000 Hz

Baud-Rate PAM4 Clock and Data Recovery (CDR)

Author: Soumobrata Ghosh
Project type: Mixed-signal digital CDR core implemented fully in synthesizable Verilog
Clock: 50 MHz
Tile size: 1 × 1

Overview

This design implements a baud-rate PAM4 Clock-and-Data-Recovery (CDR)** architecture entirely in digital logic.
It follows a classical Mueller–Müller phase detector (MMPD) structure with a proportional-integral (PI) loop filter and a digitally controlled oscillator (DCO) that generates a symbol-rate strobe.

The core tracks the phase of a four-level (PAM-4) input data stream and aligns its internal sampling instant to incoming data transitions — a technique used in **high-speed SerDes, Ethernet, and memory interface receivers.

#	Input	Output
0	DATA[0]	X[4]
1	DATA[1]	X[5]
2	DATA[2]	X[6]
3	DATA[3]	X[7]
4	DATA[4]	S[0]
5	DATA[5]	S[1]
6	DATA[6]	S[2]
7	DATA[7]	Sample_en

Input

Output

Bidirectional

DATA[0]

X[4]

DATA[1]

X[5]

DATA[2]

X[6]

DATA[3]

X[7]

DATA[4]

S[0]

DATA[5]

S[1]

DATA[6]

S[2]

DATA[7]

Sample_en

Chip location

491 Baud-Rate PAM4 Clock and Data Recovery (CDR)