This design is targetted to be used as
Basically it is a ring oscillator which is connected clock divider ckt. The clock divider can be muxed out for different frequencies
Ring oscillator Five inverters are used in chain. By shorting out0 pin to in0 and in4, the design can be configured as a ring oscillator Frequency = 1/(5*inverter cell delay)
Clock divider network Dff chain is used to introduce clock division. By using combination between s0(in1), s1(in2) , s2(in3) below we can different division at out1 fs - frequency of the clock signal
Pin description
List external hardware used in your project (e.g. PMOD, LED display, etc), if any
# | Input | Output | Bidirectional |
---|---|---|---|
0 | in | out0 | |
1 | s0 | out1 | |
2 | s1 | ||
3 | s2 | ||
4 | clk | ||
5 | |||
6 | |||
7 |