295 High-Speed-4x4-Vedic-Multiplier-for-Efficient-Arithmetic-Operations :: Quicker, easier and cheaper to make your own chip!

295 : High-Speed-4x4-Vedic-Multiplier-for-Efficient-Arithmetic-Operations

Author: Shruthi Rekhana

Description: Implements a 4x4 Vedic multiplier using Verilog.

Clock: 0 Hz

How it works

This project implements a 4x4 Vedic Multiplier based on the Urdhva Tiryagbhyam sutra from Vedic mathematics. It hierarchically uses four 2x2 Vedic multipliers to calculate the product of two 4-bit numbers (A[3:0] × B[3:0]). The result is an 8-bit product output on P[7:0].

How to test

Ensure all Verilog files are in the correct directories. Navigate to the test/ folder.

Use make to run the cocotb testbench:

cd test make

The testbench sets input values and verifies output through assertions.

You can modify the test.py file to check different inputs and behaviors.

External hardware

Not applicable — this project runs entirely in simulation and does not require external hardware.

#	Input	Output
0	A0	P0
1	A1	P1
2	A2	P2
3	A3	P3
4	B0	P4
5	B1	P5
6	B2	P6
7	B3	P7

Input

Output

Bidirectional

Chip location

295 High-Speed-4x4-Vedic-Multiplier-for-Efficient-Arithmetic-Operations