The priority encoder with parity checker module does priority encoding of a 9-bit binary input into a 4-bit binary code and displays the decimal equivalent of that code on the 7-segment display. Additionally it also does parity checking and outputs the resultant parity bit.
It has 2 modes of operation for priority encoding and for parity checking:
For priority encoding:
uio_in[1]
is low).uio_in[1]
is high).For parity checking:
uio_in[2]
is low).uio_in[2]
is high).The following table summarizes the modes:
uio_in[1] |
uio_in[2] |
Mode |
---|---|---|
0 | X | MSB priority encode |
1 | X | LSB priority encode |
X | 0 | Even parity flag |
X | 1 | Odd parity flag |
For all the modes listed above the expected inputs and generated outputs are:
ui + uio_in[0] |
uio_out[7:4] |
uio_out[3] |
uo_out |
---|---|---|---|
9-bit Binary input | 4-bit Priority code | Parity bit | 7-seg code |
The parity bit controls the DP pin of the 7-segment display.
uio_in[1]
low and observe that the priority code of {uio_in[0], ui_in}
with MSB having higher priority is output on the output pins
(uio_out[7:4]
) and on the 7-segment display connected to uo_out
.uio_in[1]
high and observe that the priority code of {uio_in[0], ui_in}
with LSB having higher priority is output on the output pins
(uio_out[7:4]
) and on the 7-segment display connected to uo_out
.uio_in[2]
low and observe that the parity bit uio_out[3]
is getting set when the input {uio_in[0], ui_in}
has even number of 1s.
The DP on 7-segment display should light up when parity bit is 1.uio_in[2]
high and observe that the parity bit uio_out[3]
is getting set when the input {uio_in[0], ui_in}
has odd number of 1s.
The DP on 7-segment display should light up when parity bit is 1.# | Input | Output | Bidirectional |
---|---|---|---|
0 | in_a[0] / IN0 | output[0] / SEG_A | in_b[0] / IN8 |
1 | in_a[1] / IN1 | output[1] / SEG_B | in_b[1] / MSB_HIGHPRMODE_n |
2 | in_a[2] / IN2 | output[2] / SEG_C | in_b[2] / EVENPARITY_MODE_n |
3 | in_a[3] / IN3 | output[3] / SEG_D | out_b[3] / PARITY_OUT |
4 | in_a[4] / IN4 | output[4] / SEG_E | out_b[4] / PRCODE[0] |
5 | in_a[5] / IN5 | output[5] / SEG_F | out_b[5] / PRCODE[1] |
6 | in_a[6] / IN6 | output[6] / SEG_G | out_b[6] / PRCODE[2] |
7 | in_a[7] / IN7 | output[7] / SEG_DP | out_b[7] / PRCODE[3] |