170 Clock Domain Crossing FIFO

170 : Clock Domain Crossing FIFO

Design render
  • Author: Kenneth Wilke
  • Description: This FIFO buffers 4-bits data asynchronously across clock domains
  • GitHub repository
  • Clock: 0 Hz

How it works

This is a FIFO that can pass data asynchronously across clock domains. This was a project I created when I was first learning logic design, and it took me a couple weeks to settle on a design that I felt was clean and reusable.

The FIFO can hold 32 4-bit values, or 16 bytes. So use them wisely and greatly!

The original design can be found at https://github.com/KennethWilke/sv-cdc-fifo

The architecture of this design was influenced by this paper written by Clifford E. Cummings of Sunburst Design by the implementation was fully written by me.

How to test

Hold write_reset and read_reset LOW while running the clock for a bit to reset, then raise to initialize the module.

Writing to the FIFO

Prepare your data on the 4-bit write_data bus, ensure the full state is low and then raise write_increment for 1 cycle of write_clock to write data into the FIFO memory.

Reading from the FIFO

The FIFO will present the current output on the read_data bus. If empty is low, this output should be valid and you can acknowledge receive of this vallue by raising read_increment for 1 cycle of read_clock.

IO

#InputOutputBidirectional
0write_clockemptywrite_reset
1write_incrementfullread_reset
2read_clock
3read_increment
4write_data0read_data0
5write_data1read_data1
6write_data2read_data2
7write_data3read_data3

Chip location

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