64 FP4 x 8-bit matrix multiplier
64 : FP4 x 8-bit matrix multiplier
- Author: ReJ aka Renaldas Zioma
- Description: 4-bit floating point (E3M0) x 8-bit matrix multiplier block
- GitHub repository
- Clock: 48000000 Hz
How it works
Matrix multiplication is implemented using a systolic array architecture.
How to test
Every cycle feed packed weight data to Input pins and input data to Bidirectional pins. Strobe Enable pin to start receiving results of the matrix multiplication on the Output pins.
External hardware
MCU is necessary to feed weights and input data into the accelerator and fetch the results.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | 2nd FP4 weight LSB | result LSB | (in) activations LSB |
| 1 | 2nd FP4 weight | result | (in) activations |
| 2 | 2nd FP4 weight | result | (in) activations |
| 3 | 2nd FP4 weight MSB | result | (in) activations |
| 4 | 1st FP4 weight LSB | result | (in) activations |
| 5 | 1st FP4 weight | result | (in) activations |
| 6 | 1st FP4 weight | result | (in) activations |
| 7 | 1st FP4 weight MSB | result MSB | (in) activations MSB |