489 Verilog OR-Gate
489 : Verilog OR-Gate
- Author: Pius Sieber
- Description: Simple OR-Gate
- GitHub repository
- Open in 3D viewer
- Clock: 0 Hz
How it works
Simple Test of Verilog Chip creation, only includes one or gate currently
How to test
Test with the first two inputs and the first output.
External hardware
List external hardware used in your project (e.g. PMOD, LED display, etc), if any
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | OR-Gate Input A | OR-Gate Output | |
| 1 | OR-Gate Input B | ||
| 2 | |||
| 3 | |||
| 4 | |||
| 5 | |||
| 6 | |||
| 7 |