295 UTOSS RISC-V core
295 : UTOSS RISC-V core
- Author: University of Toronto Open Source Students
- Description: RV32I core implementation
- GitHub repository
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How it works
To be done
How to test
To be done
External hardware
To be done
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | TBD | TBD | |
| 1 | TBD | TBD | |
| 2 | TBD | TBD | |
| 3 | TBD | TBD | |
| 4 | TBD | TBD | |
| 5 | TBD | TBD | |
| 6 | TBD | TBD | |
| 7 | TBD | TBD |