

This is a multicycle CPU that runs programs written in the BF
(BF) language. BF has eight instructions operating on a tape of byte cells and a data pointer:
> < move the pointer, + - change the cell, . , do output/input, and [ ] form loops.
The design has no on-chip RAM. Both the program and the data tape live off-chip in the RP2040's
emulated SPI RAM (Michael Bell's spi-ram-emu, which behaves like a 23LC512: SPI mode 0, 0x03 read /
0x02 write, 16-bit address). The chip reaches memory through an on-chip SPI master, so every
instruction performs at least one SPI transaction (arithmetic ops like + and - are a read-modify-write = two transactions).
Memory map (16-bit address): 0x0000–0x7FFF is instruction memory, 0x8000–0xFFFF is the data tape.
Blocks:
bf) — fetch/decode/execute control, plus a hardware bracket stack for [ ] loops.spi_ram — adapter that turns each memory request into one SPI transaction.spi_master — generates SCLK/CS, shifts the 32-bit command/address/data frame.uio[0..3]) to an RP2040 running spi-ram-emu, which provides the 64 KB memory.0x0000.rst_n low to reset, release it, then pulse start (uio[4]) high for at least one cycle.The repo's cocotb tests verify the design at multiple levels: the SPI master (Makefile.spi), the isolated BF FSM (Makefile.bf), and the full chip with a mock SPI RAM (Makefile.top).
An RP2040 (e.g. the Tiny Tapeout demo board) running spi-ram-emu to provide 64 KB of SPI RAM connected to
uio[0..3].
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | in[0] | out[0] | SPI CS |
| 1 | in[1] | out[1] | SPI MOSI |
| 2 | in[2] | out[2] | SPI MISO |
| 3 | in[3] | out[3] | SPI SCK |
| 4 | in[4] | out[4] | start |
| 5 | in[5] | out[5] | out_valid |
| 6 | in[6] | out[6] | in_valid |
| 7 | in[7] | out[7] | in_ack |