38 Wildcat RISC-V
38 : Wildcat RISC-V
- Author: Martin Schoeberl
- Description: Wildcat: a 3-stage RISC-V implementation
- GitHub repository
- Open in 3D viewer
- Clock: 25000000 Hz
How it works
It is an educational RISC-V core. This tapeout contains the bare minimum: an assembler coded blinking LED (In fact it counts up and displays the value on the 7-segment display).
How to test
Just let it run and see the 7-segment display counting up.
External hardware
None
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | in0 | out0 | inout0 |
| 1 | in1 | out1 | inout1 |
| 2 | in2 | out2 | inout2 |
| 3 | in3 | out3 | inout3 |
| 4 | in4 | out4 | inout4 |
| 5 | in5 | out5 | inout5 |
| 6 | in6 | out6 | inout6 |
| 7 | in7 | out7 | inout7 |