129 2x2 MAC Systolic array with DFT
129 : 2x2 MAC Systolic array with DFT
- Author: Julia Desmazes
- Description: 2x2 multiply and accumulate systolic array supporting signed 8 bit values with design for test infrastructure.
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- Clock: 50000000 Hz
Multiply and accumulate matrix multiplier ASIC with design for test infracture
ASIC design for a 2x2 systolic matrix multiplier supporting multiply and accumulate operations on int8 data alongside a design for test infrastructure to help debug both usage and diagnose design issues in silicon.
MAC
For faster multiplication we are using the booth radix4 algorythme with wallace trees.
If the result of the MAC operation w*i + a exeeds the ranges of the int8, they will be
clamped to int8_min and int8_max.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | tck | result_o | data_i[7] |
| 1 | data_i[0] | result_o | data_valid_i |
| 2 | data_i[1] | result_o | data_mode_i |
| 3 | data_i[2] | result_o | data_rst_addr_i |
| 4 | data_i[3] | result_o | tdi |
| 5 | data_i[4] | result_o | tms |
| 6 | data_i[5] | result_o | tdo |
| 7 | data_i[6] | result_o | result_v_o |