394 Goldcrest RISC-V
394 : Goldcrest RISC-V
- Author: Felix Roithmayr, Lucas Klemmer, Daniel Große
- Description: A microcoded RISC-V based on SUBLEQ
- GitHub repository
- Clock: 20000000 Hz
How it works
A Microcoded RISC-V processor, based on subleq.
How to test
Can't test it yet, they will follow soon.
External hardware
Two SPI memory chips, one for ROM one for RAM, as well as a UART output, 4 GPIO input pins, 4 GPIO output pins and support for 3 further SPI devices.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | UART rx | UART tx | Other SPI MOSI |
| 1 | External SPI ROM MISO | External SPI ROM SCK | Other SPI CS1 |
| 2 | External SPI RAM MISO | External SPI ROM MOSI | Other SPI CS2 |
| 3 | Other SPI MISO | External SPI ROM CS | Other SPI CS3 |
| 4 | GPIO in 0 | External SPI RAM SCK | GPIO out 0 |
| 5 | GPIO in 1 | External SPI RAM MOSI | GPIO out 1 |
| 6 | GPIO in 2 | External SPI RAM CS | GPIO out 2 |
| 7 | GPIO in 3 | Other SPI SCK | GPIO out 3 |