CPU plus MMU
needs external RAM system
external RAM
# | Input | Output | Bidirectional |
---|---|---|---|
0 | ReadData0 | AddressData0 | AddressLSB |
1 | ReadData1 | AddressData1 | WriteStrobe |
2 | ReadData2 | AddressData2 | AddressLatchHi |
3 | ReadData3 | AddressData3 | AddressLatchLo |
4 | ReadData4 | AddressData4 | unused4 |
5 | ReadData5 | AddressData5 | unused5 |
6 | ReadData6 | AddressData6 | unused6 |
7 | ReadData7 | AddressData7 | InterruptIn |