65 Delta Modulation Spike Encoding

65 : Delta Modulation Spike Encoding

Design render
  • Author: John Madden
  • Description: Delta Modulation for Spiking Neural Networks (SNN) based on snnTorch's implementation.
  • GitHub repository
  • Clock: 10000000 Hz

How it works

A spike is generated if the difference between the current and previous data inputs is greater than a specified input threshold. The design is meant to mimic the implementation of delta modulation in the snnTorch python package. Each clock cycle is treated as an input/output, therefore there can be consecutive spikes that appear to be constantly high.

The input parameter, off_spike, enables spike generation when negative threshold is exceeded. A negative spike is represented by spike[1] = 0. A positive spike is represented by spike[0] = 1.

All numerical inputs and outputs are unsigned 4-bit integers. You are able to (1) input the data value, the input (2) the threshold for a spike to be generated, and (3) a value for the previous register for debugging.

The previous data register is included to be facilitate debugging with the ability to read the current value in the register and force the register to a specific value.

How to test

The module is intended to have a digital input, such as an ADC with a parallel output that is directly fed into the data input with a shared clk signal. The threshold is meant to be tied to a constant value. The module outputs through spikes net.

For simpler testing, the input does not need to be matched to the clk. With the threshold set, data can be changed and spikes can be viewed on an oscilloscope.

IO

#InputOutputBidirectional
0input threshold bit 0spike bit 0parameter off_spike
1input threshold bit 1spike bit 1input load_prev bit
2input threshold bit 2nc, constant output lownc, constant output low
3input threshold bit 3nc, constant output lownc, constant output low
4input data bit 0reg prev bit 0input force_prev bit 0
5input data bit 1reg prev bit 1input force_prev bit 1
6input data bit 2reg prev bit 2input force_prev bit 2
7input data bit 3reg prev bit 3input force_prev bit 3

Chip location

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