518 Field Programmable Neural Array

518 : Field Programmable Neural Array

  • Author: Reto Stamm
  • Description: A collection of 50 interconnected simulated leaky neurons that can be programmed to do cognitive tasks.
  • GitHub repository
  • Clock: 10000000 Hz

How it works

Neuromorphic neural nets are more power efficient than traditional machine learning. It replicates an array of leaky neurons, a simple structure that exists in the brain. This design defines a Field Programmable Neural Array (FPNA). (1)

A mental model for a leaky neuron is a capacitor that drains at some rate. It gets charged up by some amount (its weight) whenever an input (a dendrite) receives a pulse from somewhere else. It sends a pulse (fire) its output (axon) when it reaches a specified level.

This circuit contains an array of 5*10 interconnected, heavily simplified configurable neuron blocks (CNBs). Instead of continuous weights, we have three bits per weight. Instead of a continuous decay of the charge in the capacitor, it halves at a somewhat configurable interval. Each CNB has its own set of weights, and a somewhat configurable rate of decay. In this design, each CNB had 4 inputs (dendrites), each with its own weight, one output (axon), and a choice of 8 different time decays.

An array of neuromorphic CNBs (Configurable Neuron Blocks). Each CNB has a 4 inputs, and each input has an associated weight that gets added to the CNBs membrane potential whenever the relevant input fires. When a CNB reaches a treshhold (rolls over, in this case), it fires and sends a pulse to 3 of its neighbours. Each CNB is subscribed to one of 8 decay clock tools.

The configuration data (Bitstream, or BS), including all the weights, the desired timing divisions, and the weights for each CNB are shifted in through the bs_in pin when the config_en pin is high. The BS can be read back from the bs_out pin.

The naxon tool is an example that shows how to train a neural network, generate all the relevant data and the BS that is needed to configure that model into this design https://github.com/retospect/naxon. More up-to-date design documents may also be found there.

References (1) Eshraghian, Jason K., Max Ward, Emre Neftci, Xinxin Wang, Gregor Lenz, Girish Dwivedi, Mohammed Bennamoun, Doo Seok Jeong, and Wei D. Lu. 2023. “Training Spiking Neural Networks Using Lessons From Deep Learning.”

How to test

After reset, clock in the bitstream to configure all the weights and stuff. Then clock in the test data from the generated test bench from naxon, and see the appropriate answer come out!

Picture

IO

#InputOutputBidirectional
0dendritic input 0output axon 0reset_nn reset neural network (active high)
1dendritic input 1output axon 1bs_in bitstream readout
2dendritic input 2output axon 2bs_out bitstream input
3dendritic input 3output axon 3config_en - shift bitstream
4dendritic input 4output axon 4output axon 8
5dendritic input 5output axon 5output axon 9
6dendritic input 6output axon 6dendritic input 9
7dendritic input 7output axon 7dendritic input 8

Chip location

Controller Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux Mux tt_um_chip_rom (Chip ROM) tt_um_factory_test (TinyTapeout 05 Factory Test) tt_um_loopback (TinyTapeout 05 Loopback Test Module) tt_um_Leaky_Integrate_Fire_nfjesifb (Leaky Integrate and Fire Neuron Model) tt_um_topModuleKA (Time Multiplexed Neuron Ckt) tt_um_sap_1 (SAP-1 Computer) tt_um_lif (Leaky Integrate-and-Fire Neuron (Verilog Demo)) tt_um_jleugeri_ticktocktokens (TickTockTokens) tt_um_LSNN (Spiking LSTM Network) tt_um_if (Integrate-and-Fire Neuron. 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tt_um_sunaofurukawa_cpu_8bit (cpu_8bit) tt_um_vga_clock (VGA clock) tt_um_seven_segment_seconds (7 segment seconds (Verilog Demo)) tt_um_frequency_counter (Frequency counter) tt_um_rgb_mixer (RGB Mixer) tt_um_MichaelBell_spi_peri (SPI Peripheral) tt_um_multiplexed_clock (Multiplexed clock) tt_um_psychogenic_shaman (Shaman: SHA-256 hasher) tt_um_yubex_metastability_experiment (metastability experiment) Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available Available 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