235 Matrix Vector Multiplication Accelerator

235 : Matrix Vector Multiplication Accelerator

  • Author: Mathias Eriksen
  • Description: This project takes in a 3x3 weight matrix in Compressed Sparse Row format, value is quantized and 8 bits long. It also takes in the corresponding 3 bit spike train. It then computes the matrix vector multiplication product and outputs the resulting vector on the output line
  • GitHub repository
  • Clock: 10000000 Hz

How it works

Uses a set of registers and flags from the CPU to fetch the weight matrix in CSR format as well as the spike train. The values are passed in one at a time, and the entire matrix is loaded into registers that are internal to the IC

Once the full sparse matrix and spike train are loaded in, an algorithm is used to compute the resultant vector of the matrix vector multiplication of the weight matrix and the spike train

Finally, the output vector is transmitted on the output line, along with a flag bit which flips each time a new value is sent out.

How to test

After reset, send values in CSR format using the input bits described below. Send a value by toggling the sending CPU flag for one clock cycle while the values are in their respective registers. Repeat for the entire matrix, toggling the sending CPU flag low between each value. Then, check the return values by waiting for the sending out flag from the IC to flip. After the first flip, the other two values will be sent on each clock edge.

IO

#InputOutputBidirectional
0Input Value bit 0Output Value bit 0FETCH Ready flag (out)
1Input Value bit 1Output Value bit 1Sending out flag (out)
2Input Value bit 2Output Value bit 2Done sending flag (in)
3Input Value bit 3Output Value bit 3Sending CPU flag (in)
4Input Value bit 4Output Value bit 4Column Value bit 0
5Input Value bit 5Output Value bit 5Column Value bit 1
6Input Value bit 6Output Value bit 6Row Value bit 0
7Input Value bit 7Output Value bit 7Row Value bit 1

Chip location

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