This Verilog module defines a 10-bit Linear Feedback Shift Register (LFSR). It features clock (clk
) and reset (rst
) input pins. The output pin (out
) delivers a pseudo-random sequence based on clock edges and reset conditions. It's designed for digital applications requiring pseudo-random sequence generation and pattern generation.
We test it on Vivado and open sources (OpenROAD and OpenLane).
defaults
# | Input | Output | Bidirectional |
---|---|---|---|
0 | clk | out | |
1 | rst | ||
2 | |||
3 | |||
4 | |||
5 | |||
6 | |||
7 |