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Digital Design Guide
Getting started with our digital design tool
Holidays
Logic Gates
Logic Puzzle - Flip Flop
Logic Puzzle - Edge Detect
Logic Puzzle - Full Adder
Logic Puzzle - Padlock
Customisable Design - Padlock
Customisable Design - UART
Customisable Design - 7-Seg
Generating Wokwi designs from truth tables
How do semiconductors work?
Introduction to SiliWiz
Draw a Resistor
Parasitics
Voltage Divider
Draw a capacitor
Draw an N MOSFET
Making a logic inverter
Draw a P type MOSFET
Draw a CMOS inverter
Making ASICs
Working with HDLs
Important!
FPGA to ASIC
HDL resources
HDL templates
Testing your design
Teaching resources
FAQ
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English
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Tiny Tapeout 02
> 38 YaFPGA
38 : YaFPGA
38 YaFPGA
38 : YaFPGA
Author: Frans Skarman
Description: Yet another FPGA
GitHub repository
Most recent GDS build
HDL project
Extra docs
Clock: 1000 Hz
External hardware:
How it works
TODO
How to test
TODO
IO
#
Input
Output
0
clock
output0
1
input1
output1
2
input2
output2
3
input3
output3
4
input4
none
5
config data
none
6
config clock
none
7
none
none